The present invention relates generally to semiconductor-based sensors and specifically to silicon on insulator (SOI) based sensors.
A diaphragm type silicon based pressure sensor will be used as an example to describe a problem with sensors in the past. Such pressure sensors typically include piezoresistors positioned to sense strain associated with pressure and arranged in a Wheatstone bridge to which a direct current voltage is applied. The output voltage of the bridge is representative of the pressure that is being sensed. A power up drift (PUD) phenomena has been observed in silicon-based sensors that is not explained by a small thermal rise that may occur after power is applied to the sensor. A PUD effect as great as 0.05% of full scale has been observed.
The PUD phenomena is apparently a result of mobile ions present either on the surface of the silicon chip or within the silicon dioxide passivation layer, which have one preferred configuration with power off and a second preferred configuration when power is applied. In other words, these ions are mobile in response to the application of voltage to the silicon chip. As the charges move they apparently affect the characteristics of the circuit elements on the chip. The charges may reside in any of a number of locations in the integrated circuit. They may be in the silicon, in insulating layers on or under the silicon, at the interfaces between two of these layers, or at the surface of the silicon chip. Sensors, including pressure sensors, are often designed with a bridge configuration to minimize this and other performance limitations. In a bridge configuration, the change of any one element resulting from the redistribution of charges on power up is not significant as long as its balancing element undergoes the same change. Therefore, great care is usually taken in the design of a sensor to insure that the individual elements of the bridge are as identical as possible. The power-up drift of the bridge output xe2x80x9cresetsxe2x80x9d itself after the power is removed to the value that existed before power was applied. The time required after power is applied for the PUD to stabilize is typically less than the time required for the sensor to xe2x80x9cresetxe2x80x9d after the power is removed.
Silicon-on-insulator (SOI) based sensors offer several performance advantages over conventional bulk-silicon based sensors due to the elimination of the p-n junction. In bulk silicon, the p-type piezoresistors are implanted or diffused into an n-type epitaxial layer, which results in the formation of a p-n junction. The reverse current leakage of a p-n junction increases with temperature (approximately doubles every 10xc2x0 C.), which ultimately limits the operating temperature to typically 125xc2x0 C. To minimize the effect of the reverse current leakage, which typically shunts the piezoresistor element, on performance, the value of the piezoresistive bridge elements are typically limited to 40K ohm maximum to maintain quality performance over temperature.
In SOI, however, the piezoresistor elements are isolated from the silicon substrate by an insulation layer thereby eliminating the p-n junction and it""s associated reverse leakage current. The high temperature operating limit of SOI material is therefore significantly increased to a range of 200xc2x0 C. to 400xc2x0 C. depending on the metalization system, packaging and materials and other variables.
SOI sensors also allow the piezoresistive bridge impedance to be increased to as high as 200K ohm with equivalent performance. The higher impedance reduces the sensor power requirements proportionally. For example, increasing the bridge impedance from 40K ohm to 200K ohm reduces the sensor power requirement by a factor of five. These larger impedance values can be achieved without significantly increasing the physical area of the piezoresistor element. This is accomplished in two ways. First, the effective thickness of the piezoresistor element can be formed to be significantly thinner than that formed in bulk silicon which results in a higher sheet resistivity (ohms per square) that is inversely proportional to the thickness. Secondly, the impurity concentrations of the diffused or implanted piezoresistor can be reduced, without performance degradation, which also results in an increase in sheet resistivity. The combination of the two methods can result in a five-fold increase in sheet resistivity for the same form of the resistor area.
The combination of high temperature operation and power reduction allows SOI based sensors to be used in many new applications that are beyond the capability of bulk-silicon based sensors. Where the sensor application is such that reduced measurement accuracy is acceptable or where a period of warm-up time is permissible, the power-up-drift phenomena may not be a problem. However, numerous applications require the sensor to met specifications within a very short time, (for example, a few seconds or less,) after power is applied. Thus there is a need for a silicon-on-insulator sensor configuration that greatly reduces the cause(s) of power-up drift.
The present invention solves these and other needs by providing a solution for reducing the power up drift observed in the output of Wheatstone bridge configurations of SOI based sensors. In the preferred embodiment of the present invention, a sensor has a layer of silicon formed on a silicon substrate, the layer of silicon having an insulation layer dividing the layer into an upper and lower layer. Within this upper layer, a plurality of resistors are formed, connected in a bridge arrangement. The preferred embodiment also includes a means for supplying a first voltage to the bridge arrangement and a means for supplying a second voltage to the lower layer of silicon. The level of the second voltage is selected to reduce the power up drift.